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Verplex Ships Full-Chip Formal RTL Design Verification Tool That Eliminates Learning Curve
MILPITAS, Calif.--(BUSINESS WIRE)--Nov. 20, 2000--
Verplex(TM) Systems, Inc., the electronic design automation (EDA)
company known for its formal verification software, today unveiled
BlackTie(TM) functional checker, a full-chip, multi-million gate
capacity tool that accelerates the verification of system-on-a-chip
(SOC) designs.
BlackTie was designed to be easy to use, eliminating the learning
curve normally associated with formal register transfer level (RTL)
design verification technology. It provides a means for exhaustive
verification early in the design cycle when changes are easily fixed
and less costly, and offers designers full-chip speed and capacity. In
a recent customer engagement, for example, it verified more than
300,000 functional properties of a 2.7 million gate design in
approximately 20 minutes using a standard Unix workstation.
An open source assertion monitor library enables simulation and
formal verification to operate seamlessly, rounding out BlackTie's
feature set.
It eliminates the learning curve by verifying monitors, a concept
already familiar to simulation users. ``Our goal with BlackTie has been
to make formal verification an easy-to-use design methodology, and as
much a part of the design environment as logic simulation,'' notes C.
Michael Chang, president and chief executive officer of Verplex.
BlackTie provides exhaustive verification early in the design
cycle to find as many RTL problems as possible since bugs are harder
to fix downstream. Designers can formally check assertion monitors in
their designs to find deeply embedded bugs, where integration-level
test vectors may have little control or may not be sufficiently long
enough to propagate errors to an observable output.
Formal RTL verification software on the market today requires the
designer to break the design into smaller blocks of roughly 50,000
gates. BlackTie is able to verify hundreds of blocks that size
collectively, catching many functional problems caused by SOC-level
integration not found by other verification methods.
An open source assertion monitor library written in the Verilog
Hardware Description Language (HDL) makes BlackTie as easy to use as
simulation. The library enables, for the first time, simulation and
formal verification to operate seamlessly. The same monitors written
for simulation can be verified using BlackTie. When verifying monitors
with BlackTie, test vectors are not required, coverage is exhaustive
and the diagnosis is automatic. (In an accompanying news release issued today, Verplex announced
that it is placing the verification library used by BlackTie in the
public domain. The library can be downloaded at no charge from the Web
Site located at: http://www.verificationlib.org.)
BlackTie automates the checking of global, commonplace errors. For
instance, it automatically checks for contention problems in every bus
of the design, eliminating the need for manual placement of assertion
monitors to specifically check for these problems.
Other automatic checks include: asynchronous clock domain
crossings; dead-end states; conflicting values loaded to multi-port
registers; simultaneous set and reset conditions; mutual exclusivity
checks; and tri-states that are stuck in a particular state.
With the addition of BlackTie, Verplex offers an independent
verification platform that validates the correctness of full-chip,
multi-million gate designs at the initial RTL stage. The platform
ensures that correctness to the final gate or transistor level using
the Tuxedo(TM) LEC equivalence checker and Tuxedo(TM) LTX transistor
extraction tool.
Pricing and Availability
BlackTie is shipping today and supports Hewlett Packard, Sun
Microsystems and Linux operating systems. It is available at a price
of $75,000.
More information on BlackTie and other Verplex software products
can be found at www.verplex.com, or contact Dino Caporossi, director
of marketing at Verplex. He can be reached at (301) 390-2718 or via
email at dino@verplex.com.
About Verplex
Verplex Systems Inc. is an electronic design automation (EDA)
company focused on delivering the highest speed, highest capacity and
easiest to use formal verification products for complex system-on-chip
(SOC) design. Founded in 1997, it is privately held and funded by
leading venture capital firms. Corporate headquarters is located at
300 Montague Expressway, Suite 100, Milpitas, Calif. 95035. Telephone:
(408) 586-0300. Facsimile: (408) 586-0230. Email: info@verplex.com.
Online information is found at its web site: http://www.verplex.com.
Verplex, BlackTie and Tuxedo are trademarks of Verplex Systems
Inc. All other companies and products referenced herein are trademarks
or registered trademarks of their respective holders.
Contact:
Verplex Systems, Inc.
Nanette Collins
(617) 437-1822
nanette@nvc.com
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